HDL Co-Simulation

In HDL Co-simulation (also called simulation acceleration), the testbench executes in the HDL (Verilog or VHDL) Simulator, while the design is emulated. Synchronization is performed at every signal event between the testbench and DUT in ZeBu.

C++ Co-Simulation

In C++ Co-simulation, the testbench is written and executed in C++ for greater testbench performance. Signals are synchronized at clock boundaries. Clocks advance under control of the C++ testbench.

Transaction-Level Co-Emulation

In Transaction-Level Co-Emulation, the testbench is written in C++, SystemC or SystemVerilog. Packets of data (transactions) are exchanged between the testbench and the DUT. Encoding and decoding of packets into signals for the DUT is performed in hardware, at very high speed (faster than the DUT, typically at 50 MHz). In the example, each packet corresponds to a valid pixel.

Typical result: 50 kHz (100X RTL simulation)

Sample Verilog code:

Typical result: speed in the 200 kHz range

Sample C++ code:

Typical result: speed in the tens of MHz range

Sample C++ code:

always @(posedge clk) begin
   if (!ce && !we) begin
      mem[add] <= data;
      $displayPixel(add, data);
   end
end

Signal &ce = *(top->ce);
Signal &we = *(top->we);
Signal &add = *(top->add);
Signal &data = *(top->data);

while(1) {
   if(!ce && !we){
      mem[add] = data;
         displayPixel(add, data);
   }
   top->run(1);
}

Port *rcv_port;
unsigned int *msg;


while(1) {

   while(!rcvPort->isPossibleToReceive());
   msg = rcvPort->receiveMessage();
   *add = msg[1] & 0x1fff;
   *data = msg[0];
   displayPixel(add, data);
}