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SEE ALSO

Datasheet: ZeBu-Blade2

Demo: Linux Boot

Solution: Super-Block Verification

Solution: HW/SW Co-Verification

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ZeBu-Blade2 Fast ASIC Desktop Emulator

News: EVE Unveils ZeBu-Blade2 Hardware-Assisted Verification Platform

The ZeBu-Blade2 hardware-assisted verification platform is the newest member of the ZeBu emulation family, and the first based on Xilinx Virtex6-LX760 field programmable gate arrays (FPGAs). Emulating single-user designs up to 18 or 32 million ASIC gates at up to 40MHz in a compact chassis, ZeBu-Blade2 represents a paradigm shift in emulation, from the lab to the desktop for the entire design team.

The ZeBu approach to hardware/software co-verification combines the best aspects of traditional hardware emulation with those of FPGA prototyping systems into a single, unified environment for both ASIC/SOC debugging and embedded software validation. By sharing the same verification platform and the same design representation, hardware design and software development teams can share the same system and design representation, and can easily collaborate when debugging complex hardware/software interactions. The net effect is that hardware/software integration takes place much earlier in the design cycle, thereby reducing silicon respins and accelerating time to market.

Features

  • 40-nm technology: Using 40-nm Xilinx Virtex-6 LX760 FPGAs
  • Design Capacity: 18M (5xLX760) or 32M (9xLX760) ASIC gates; 4GB system memory plus local memory
  • Emulation Speed: Up to 40 MHz design clock in both transaction-based and in-circuit emulation
  • High Bandwidth Test Environment: PCI-Express connectivity to host PC provides high bandwidth for Streaming Transactors, Software Checkers, Assertion Output, and Waveform Generation
  • Rapid setup: Completely automated compiler, starting from ASIC RTL, requiring no RTL modifications; supports compute farms and load sharing for parallel compilation
  • zFAST: ZeBu Fast Synthesis for high speed, parallel, incremental synthesis with memory inference and preservation of RTL names
  • Memory Compiler: Supports an unlimited number of ports, scriptable for easy ASIC library conversion
  • Comprehensive Debugging: Run-time access to all RTL signals, both sequential (register and memories) and combinational, without recompilation and with and unbound trace window; Pre-compiled probes for high speed tracing and software-based checkers; Synthesizable SystemVerilog Assertion support
  • Integrated with popular Third-Party Verification and System Level Tools: Co-simulation with commercial HDL simulators and ESL tools, integration with waveform viewers and interactive debuggers LX FPGAs from Xix
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