THE LEADER IN HARDWARE/SOFTWARE CO-VERIFICATION 
SystemVerilog Assertions
EVE's ZeBu fast emulators now support SystemVerilog Assertions in emulation. Embedded and bound synthesizable SystemVerilog Assertions are supported using zFAST (ZeBu FAst SynThesis). Similarly to ZEMI-3, SystemVerilog Assertions improve the debugging process by accelerating the location of bugs and by minimizing the size of waveform files needed to isolate the bug.
Features
- Supports the synthesizable subset of SystemVerilog Assertions
- Bound and embedded Assertions can be compiled into the emulator at the design, module, instance and assertion level
- Assertion failures, starts and ends, and successes can be reported live or via post-processing
- Assertions can be used as a logic analyzer trigger
SEE ALSO
- Product: ZEMI-3
- Product: ZeBu Probes
SVA Support
