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News! EVE’s ZeBu-Server Supports Smart Debug Methodology

ZeBu Smart Debug Methodology Overview

EVE's ZeBu fast emulators come equipped with a comprehensive suite of debugging features, which enable you to quickly find and correct bugs in your ASIC design. However, simply having this technology is not sufficient to track down complex bugs that lie billions of cycles deep in the state space. You also need an effective "Smart Debug" methodology in order to efficiently achieve debug convergence as you reproduce tests and filters billions of cycles of raw data into relevant debug information.

Traditional Emulator Debugging Techniques

Traditional emulator debugging is based on the use of Logic Analyzers (LAs) and triggers, and is typically used in an In-Circuit Emulation (ICE) environment. Signals are routed to an on-board trace memory, and the signal capture is initiated via the LA. This technique has the advantage of performing at full emulation speeds, but also has the disadvantage of being limited to a fixed trace window. The limited trace window means that selecting your trigger is critical to the success of your debugging, particularly in ICE environments where the test may not be deterministic, meaning that the failure point or trigger may occur at a different cycle.

Transaction-based Emulation

Transaction-based ZeBu emulation provides a cycle-accurate, fully reproducible environment which is the enabler for the Smart Debug methodology. Transactors can even be used to provide Smart Debug capabilities for non-deterministic ICE environments!

Leveraging Multiple Levels of Abstraction

The ZeBu debug technology offers the user multiple forms of design access, which trade-off between accessibility and run-time performance. The ZeBu Smart Debug methodology leverages this concept, first using the highest speed probes and tracers to initially isolate the time and location of the failure, and then using a wider range of assertions, checkers, and probes to specifically identify the trigger and sub-system in question. Finally, complete waveforms can be generated for the sub-system, and the designer can perform a detailed analysis.

 Debug Convergence

Multi-Phase, Multi-Pass Methodology

The ZeBu Smart Debug Methodology is a Multi-Pass methodlogy that can be broken up into three phases:

  • 1) Preparation Phase - Before emulating your design, compile Static Probes, Flexible Probes, and SystemVerilog Assertions into the design. Add ZEMI-3 tracer transactors and LA triggers to the Reconfigurable Testbench (RTB).
  • 2) Investigation Phase - After a test failure, reproduce the test, and use the ZeBu run-time environment, the SW debugger, and the pre-compiled probes, assertions and tracers/checkers to isolate the exact trigger/cycle of failure, as well and the suspect sub-system(s).
  • 3) Detailed Debug Phase - Reproduce failing test or leverage save/restore to reach trigger/failure point very quickly, and then enable complete waveform generation for the sub-system(s) using Dynamic Probes. Perform detailed debugging with your favourite waveform viewer.

 

 

ZeBu Smart Debug Phases

Next: Smart Debug Methodology: Preparation Phase