SEE ALSO
- Prev: Smart Debug Methodology: Detailed Debug Phase
- Product: ZEMI-3
- Product: ZeBu Debug Features
- Product: ZeBu Probes
- Product: SystemVerilog Assertion Support
- Solutions: Transaction-Based Verification
- Datasheet: Next Gen System Validation Using Transactors
ZeBu Smart Debug Methodology: ICE Debug
In-Circuit Emulation (ICE) environments can potentially pose two problems for debugging:
- Requirement for fixed timing: ICE clocks (e.g. JTAG TCK) may not be tolerant to clock stalling or stoppage, breaking the connection between the emulator and the target system. This would prevent the usage of Dynamic Probes and Save & Restore for detailed waveform generation and debugging.
- Non-determinism in testing: ICE environments are rarely deterministic, meaning that the exact same test is not reproducible. This is also an issue for transactor environments running at the Application-Level, where the transactors are non-blocking.
In order to utilize the ZeBu Smart Debug Methodology for ICE and Application-Level test environments, the first step is to create an environment which can reproduce the original test exactly. This requires "sniffing" the input activity to the design during the original test, and then re-injecting the same input activity to the design via blocking transactors. The new transactor environment has no dependency on the ICE target system, is cycle accurate and reproducible, and therefore fully compatible with the ZeBu Smart Debug Methodology.
"Sniffer" and Re-injector Transactors
ZEMI-3 can be used to easily create high-speed transactors which "sniff" the top-level input activity on small design interfaces, such as JTAG, in an otherwise Synthesizable Testbench (STB) environment. The input activity can then be re-injected into the design via a second ZEMI-3 transactor, reproducing the SW debugger's JTAG commands exactly.