SEE ALSO
- Prev: Smart Debug Methodology: Overview
- Next: Smart Debug Methodology: Investigation Phase
- Product: ZEMI-3
- Product: ZeBu Debug Features
- Product: ZeBu Probes
- Product: SystemVerilog Assertion Support
- Solutions: Transaction-Based Verification
- Datasheet: Next Gen System Validation Using Transactors
ZeBu Smart Debug Methodology: Preparation Phase
The first step in the ZeBu Smart Debug Methodology is the Preparation Phase. This phase occurs before you run even a single test, during the initial bring-up and compilation of the design. During this phase, compile Static Probes, Flexible Probes, SystemVerilog Assertions, ZEMI-3 tracer transactors, and LA triggers into the system. These pre-compiled options remain dormant during regressions, and can be enabled at run-time, once a failure has been discovered.
Selecting the appropriate signals for probes and triggers requires careful planning. The verification plan for your design is a valuable resource to help you decide which register and signals to choose. Changes to the pre-compiled probe and trigger set will require an incremental compilation, but remember that any register and signal in the design can later be accessed at run-time via Dynamic Probes, without any re-compilation.
Selecting Static Probes
Static Probes enable access to critical signals at full emulation speed, up to 30MHz. Static Probes can generate waveforms using ZeBu's on-board trace memory, and can also be used as logic analyzer triggers, or as inputs to custom transactors using ZEMI-3. Use Static Probes on critical busses and registers that may be accessed frequently by the testbench or monitors. Common locations for Static Probes include: the processor program counter, transactor I/O, and small design I/Os (e.g. the JTAG/UART interface).
Selecting Flexible Probes
Flexible Probes can be added to the design in greater numbers than Static Probes - up to over 30k/FPGA. They only impact run-time performance when enabled for tracing, capturing signals in the low MHz. Flexible Probes are compiled and enabled by group, to minimize the impact. Use Flexible Probes on design interface signals and for major functional blocks. Common locations for Flexible Probes include: the memory controller, PCIe sub-system, and all design I/O for the first 3-4 levels of hierarchy.
Flexible probes can also be accessed via a software testbench, and can be used to implement software-based logic analyzers and checkers. New logic analyzer functions can be written without any need for re-compilation.
SystemVerilog Assertions
ZeBu emulators support the synthesizable subset of SystemVerilog Assertions (SVAs) with zFAST, ZeBu Fast Synthesis. Assertions can be compiled into the emulator at the design, instance, and assertion level, and then subsequently enabled/disabled at run-time. SVA reports can be generated live, or post-processed, and SVAs can also be used as triggers for tracing and clock control.
ZEMI-3 Transactors
ZEMI-3 is a behavioral SystemVerilog compiler that makes it extremely easy to write transactors and Synthesizable Testbench (STB) components. Use ZEMI-3 to create complex HW logic analyzer components, or to perform high speed monitoring of critical signals (e.g. those selected as Static Probes). ZEMI-3 can also be used to create tracer and player transactors, which can be used to reproduce ICE and non-deterministic application level tests.