SEE ALSO
- Prev: Smart Debug Methodology: Investigation Phase
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- Product: ZEMI-3
- Product: ZeBu Debug Features
- Product: ZeBu Probes
- Product: SystemVerilog Assertion Support
- Solutions: Transaction-Based Verification
- Datasheet: Next Gen System Validation Using Transactors
ZeBu Smart Debug Methodology: Detailed Debug Phase
The final phase of the ZeBu Smart Debug Methodology is the most straightforward. Once the time and location of the failure has been isolated into a usable set, simply re-run the test up to the identified clock cycle or trigger point, and then generate waveforms for the entire module or sub-system in question. Then use your favorite waveform and source code viewer to perform a detailed analysis of the problem.
Enabling Dynamic Probes
Dynamic Probes are easily enabled via zRun or the testbench, and provide access to every register in the design, without the need for any re-compilation. Combinational signals are simulated along with Dynamic Probes, providing waveforms for every register and signal within the module or sub-system being investigated.
When reproducing a test for Dynamic Probe waveform generation, ZeBu's Save & Restore feature can be used to jump ahead in the cycle count and state space, saving valuable time in the Detailed Debug Phase.
Fixed Timing and Application-Level Tests
There are some emulation environments for which Dynamic Probes and Save & Restore capabilities may not be initially usable. These include cases where the timing is fixed (e.g. ICE environments not tolerant to clock stalling) or where the test is running in an application mode (e.g. transactor running in non-blocking/untimed operation). For situations such as these, we first need to create a reproducible environment, before the Smart Debug Methodology can be applied.