Looking for a cycle-accurate model for the latest ARM cores?
ZeBu can easily turn RTL or a logic tile into a cycle-accurate model that you can use in any ESL environment, running at many MIPS.
ARM Core Integration
EVE offers a broad array of support for ARM cores/models, enabling HW/SW co-verification and concurrent HW/SW debugging with full RTL design access and interactive SW debugging.
ARM Soft Cores
ZeBu supports ARM synthesizable RTL models by compiling and mapping them onto the Xilinx FPGAs within the emulator. ARM SystemC models execute directly on the ZeBu host PC and can interface to the emulated SoC via a transactor (e.g. AMBA AXI). ZeBu synthesizable transactors provide cycle accuracy while maintaining high performance, by executing the Bus-Functional Model (BFM) in the ZeBu Reconfigurable TestBench (RTB) hardware, and leveraging a wide bandwidth, high speed interface to the host PC.
ARM Hard Cores
ARM hard cores such as logic tiles (module with one FPGA programmed via SMM) and core tiles (ARM core tile mounted with ARM test chip) are supported by the ZeBu Direct-ICE interface.
SW Debugging
For HW/SW co-verification and concurrent HW/SW debugging, a connection between the ARM core and the SW debugger is required. Once again, EVE offers a broad array of support for ARM core SW debugging, including:
- SW debug via ARM ISS (built-in connection)
- SW debug via ARM Soft IP (RTL) Core (JTAG connector through ZeBu Direct/Smart-ICE pins)
- SW debug via ARM Soft IP Core (JTAG transactor e.g. ARM VSTREAM)
- SW debug via ARM Hard Core (dedicated JTAG port on tile)
EVE also provides consulting services to develop custom hard IP core modules and test chip modules.