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Hardware-Assisted Simulation Acceleration
Functional verification is a daunting task. As chip densities grow, so does the complexity of verifying the functional behavior of the design. To compound the problem, the complexity of functional verification grows faster than design density because of the additional interaction between a growing combination of functional units and 3rd Party IP blocks within a design. To get products to market in a timely fashion, teams either have to take the risk to tape-out early with less confidence that verification is complete or find more effective ways to test more.
EVE's Simulation Acceleration Model
Traditional software simulators offer very convenient use models, relatively low cost, and sophisticated debugging capabilities. Unfortunately, they suffer dramatic throughput deterioration as the design size increases. The bottom line is that software simulators are running out of steam for the current and future generations of chip designs. As the clock frequencies of CPUs are reaching their limits and processor vendors move to multi-core products instead, the performance gap is only guaranteed to get wider.
All ZeBu emulators are capable of HDL co-emulation, functioning as a simulation accelerator to provide more simulation throughput. Requiring no changes to your existing verification environment, it provides immediate RTL acceleration even for testbenches that rely on the most advanced verification methodologies available today. Furthermore, the use of ZeBu emulators in HW verification can be extended to the transaction-level, enabling even greater performance gains. ZeBu emulators are compatible with advanced verification methodologies such as VMM, OVM and UVM.
