Transaction-Level Modeling
ZeBu allows you to simulate a design at very high clock frequencies, but to for it to be a complete solution, you must be able to interact with your design without slowing it down. Transaction-Level Modeling provides checkers, monitors and data generators with the throughput your DUT requires.
Benefits
- Speed: ZeBu transactors offer the highest performance on the market. Transaction-level performance is easily characterized by two parameters: bandwidth and latency. ZeBu can stream data to and from a design at up to 800 Mbit/s. Latency directly dictactes how many messages can be processed by a testbench. ZeBu reaches up to 500,000 round-trip messages per second.
- Reuse: ZeBu separates the implementation of the protocol(s) from the generation of test scenarios, so testbenches can be easily assembled from building blocks and new chips benefit from reusable transactors.
- Easy: You can either buy off-the-shelf transactors for most common protocols, or design your own if you have a unique interface/application. The main part of a custom transactor is the Bus Functional Model (BFM) or Finite State Machine (FSM) for your interface, which can be written in standard Verilog or VHDL RTL, or in behavioral SystemVerilog using ZEMI-3, EVE's transactor compiler. Most likely, you already have a similar piece of code that can be easily converted to act as a transactor.
Languages
Various languages can be used for the transaction-based testbench:
- C/C++/SystemC testbench: ZeBu transactors are adapted from the SCE-MI standard and follow a simplified/optimized API so that you can be up and running with only a few lines of code. An API fully-compliant with SCE-MI is also available if compatibility across emulation platforms is more important than performance.
- SystemVerilog testbench: ZeBu transactors can be integrated with SystemVerilog testbenches using the standard ZeBu API, the SystemVerilog DPI, a SystemVerilog class, and the Verification Methodology Manual (VMM) Hardware Abstraction Layer (HAL) from Synopsys.
In addition to standard RTL (Verilog and VHDL), various tools allow you to create the FSM of a ZeBu transactor, including:
The ZEMI-3 Transactor Compiler from EVE also enables the easy creation of transactor FSMs, but also has the added benefits of:
- Supporting behavioral constructs, such as implicit state machines, wait states and mixed clock edges
- Automatic implementation of the transactor communication infrastruture
- Performance optimization via streaming, prefetching
SEE ALSO
- Demo: HDL Co-sim vs. Cycle vs. Transaction-Based Emulation
- Product: Validation IP
- Product: ZEMI-3 Transactor Compiler
- Whitepaper: Next Gen System Validation Using Transactors
Performance and Accuracy
The concept of transactors has been used in verification for a long time. A layered testbench cleanly separates the high-level protocol functions (for instance reading and writing on a AHB bus) from the low-level implementation (toggling the control and data signals of the AHB bus). ZeBu takes the concept one step further by off-loading the low-level transaction encoding and decoding into dedicated, customizable hardware. That accomplishes two unique goals: fully cycle-accurate simulations, at a performance on par with or even higher than hooking up to real in-circuit interfaces.
