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ZeBu Smart Debug Methodology: ICE Debug

In-Circuit Emulation (ICE) environments can potentially pose two problems for debugging:

• Requirement for fixed timing: ICE clocks (e.g. JTAG TCK) may not be tolerant to clock stalling or stoppage, breaking the connection between the emulator and the target system. This would prevent the usage of Dynamic Probes for detailed waveform generation and debugging.
• Non-determinism in testing: ICE environments are rarely deterministic, meaning that the exact same test is not reproducible. This is also an issue for transactor environments running at the Application-Level, where the transactors are non-blocking and the DUT clocks run freely between transactions.

In order to utilize the ZeBu Smart Debug Methodology for ICE and Application-Level test environments, the first step is to create an environment which can reproduce the original test exactly. This requires "sniffing" the input activity to the design during the original test, and then re-injecting the input frames to the design via blocking transactors. The new transactor environment has no dependency on the ICE target system, is cycle accurate and reproducible, and therefore fully compatible with the ZeBu Smart Debug Methodology.

Prev: Smart Debug Methodology: Detailed Debug Phase

• HW / SW Co-Verification|
• Pre-Silicon Software Validation|
• Simulation Acceleration|
• SOC Emulation
• Transaction-Level Modeling|
• ZeBu "Smart" Debug|
• ESL Co-Emulation|
• Super-Block Verification
• Reconfigurable Computing|
• Processor models|
• Case studies